Ucf location constraints, Fpga connections to cpld, Cpld – Digilent 410-087P-KIT User Manual
Page 127: Fpga connections to cpld cpld

Spartan-3E Starter Kit Board User Guide
127
UG230 (v1.0) March 9, 2006
UCF Location Constraints
R
UCF Location Constraints
There are two sets of constraints listed below
–
one for the Spartan-3E FPGA and one for the
XC2C64A CoolRunner-II CPLD.
FPGA Connections to CPLD
provides the UCF constraints for the FPGA connections to the CPLD ,
including the I/O pin assignment and the I/O standard used.
CPLD
provides the UCF constraints for the CPLD , including the I/O pin assignment
and the I/O standard used.
Figure 16-2:
UCF Location Constraints for FPGA Connections to CPLD
NET
"XC_CMD<1>"
LOC
= "N18" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"XC_CMD<0>"
LOC
= "P18" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"XC_D<2>"
LOC
= "F17" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"XC_D<1>"
LOC
= "F18" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"XC_D<0>"
LOC
= "G16" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"FPGA_M2"
LOC
= "T10" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"FPGA_M1"
LOC
= "V11" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"FPGA_M0"
LOC
= "M10" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"XC_CPLD_EN"
LOC
= "B10" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"XC_TRIG"
LOC
= "R17" |
IOSTANDARD
= LVCMOS33 ;
NET
"XC_GCK0"
LOC
= "H16" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"GCLK10"
LOC
= "C9" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"SPI_SCK"
LOC
= "U16" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
# SF_A<24> is the same as FX2_IO<32>
NET
"SF_A<24>"
LOC
= "A11" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"SF_A<23>"
LOC
= "N11" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"SF_A<22>"
LOC
= "V12" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"SF_A<21>"
LOC
= "V13" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
NET
"SF_A<20>"
LOC
= "T12" |
IOSTANDARD
= LVCMOS33 |
DRIVE
= 4 |
SLEW
= SLOW ;
Figure 16-3:
UCF Location Constraints for the XC2C64A CPLD
NET
"XC_WDT_EN"
LOC
= "P16" |
IOSTANDARD
= LVCMOS33 ;
NET
"XC_CMD<1>"
LOC
= "P30" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_CMD<0>"
LOC
= "P29" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_D<2>"
LOC
= "P36" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_D<1>"
LOC
= "P34" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_D<0>"
LOC
= "P33" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"FPGA_M2"
LOC
= "P8" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"FPGA_M1"
LOC
= "P6" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"FPGA_M0"
LOC
= "P5" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_CPLD_EN"
LOC
= "P42" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_TRIG"
LOC
= "P41" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_DONE"
LOC
= "P40" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_PROG_B"
LOC
= "P39" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"XC_GCK0"
LOC
= "P43" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"GCLK10"
LOC
= "P1" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"SPI_SCK"
LOC
= "P44" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
# SF_A<24> is the same as FX2_IO<32>
NET
"SF_A<24>"
LOC
= "P23" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"SF_A<23>"
LOC
= "P22" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"SF_A<22>"
LOC
= "P21" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"SF_A<21>"
LOC
= "P20" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;
NET
"SF_A<20>"
LOC
= "P19" |
IOSTANDARD
= LVCMOS33 |
SLEW
= SLOW ;