Digilent 410-087P-KIT - Manual (Page 104)

104 www.xilinx.com Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
Chapter 13: DDR SDRAM R
The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best
access to one of the FPGA’s Digital Clock Managers (DCMs). This path is required when
using the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controller
IP core documentation is also available from within the EDK 8.1i development software
(see
“Related Resources,” page 107 ).
DDR SDRAM Connections
Table 13-1 shows the connections between the FPGA and the DDR SDRAM.
Table 13-1: FPGA-to-DDR SDRAM Connections
Category
DDR SDRAM
Signal Name
FPGA Pin
Number Function
Ad
dr
ess
SD_A12 P2 Address inputs
SD_A11 N5
SD_A10 T2
SD_A9 N4
SD_A8 H2
SD_A7 H1
SD_A6 H3
SD_A5 H4
SD_A4 F4
SD_A3 P1
SD_A2 R2
SD_A1 R3
SD_A0 T1