Rockwell Automation SA3100 Power Module Interface (PMI) Regulator - Manual (Page 41)

Resolver & Drive I/O Board 3-7
The balance calibration procedure minimizes oscillations that occur due to imbalances
between channels by adding capacitance to the sine or cosine channel. The board
calculates the capacitance value which yields the smallest velocity variations with
sine/cosine magnitudes within 1% of each other. Due to the characteristics of the
cable or to noise problems, it is possible that the magnitudes will not be within 1% of
each other. In this case, the board will calculate the capacitance value that minimizes
velocity variations. When the balance calibration procedure is completed, bit 7 of
UDC register 201/1201 will be set, and the balance value will be stored in
RES_BAL%. If the sine/cosine magnitudes are not within 5% of each other, bit 5 of
UDC register 203/1203 (Tuning Aborted Warning) will also be set.
Checking Calibration Procedure Results
As described previously, bits 6 and 7 of UDC register 201/1201 will be set to indicate
the gain and balance calibration procedures, respectively, have been completed.
These bits do not indicate that the procedures were successful or that the resulting
values are valid. After each test, check the value stored in the local tunables
RES_GAN% and RES_BAL%. If the value is near or at its maximum value, it may
indicate a problem. Refer to the SA3100 Drive Configuration and Programming
instruction manual (S-3056) for more information about these local tunables.
After the balance test, check the Tuning Aborted Warning bit (bit 5, UDC register
203/1203). This bit will be set if the balance calibration procedure was unsuccessful
or yielded unexpected results. Failures may be caused by leaving the resolver
unconnected during the procedure or using cable runs beyond the recommended
lengths (see chapter 5). Calibration procedure failures will not prevent the operation of
the drive.
3.2.2 Analog Input
The Resolver Feedback connector is used for both resolver input and analog input
signals. Refer to figure 3.2 for the connector pinout.
The analog input operates over the range of +/-10V differential (+/-30V common
mode). It is the user’s responsibility to ensure that the input signal is scaled to
conform to this range. The input is bandwidth-limited to 300 Hz nominal. The
resolution of the input is 12 bits (11 bits plus sign) or 4.88 mV per bit. The input
impedance is 1.3 megohms and is resistively isolated. If an analog tachometer is not
used, the input may be used for other purposes as long as the signal is within the
correct voltage range. The PMI processor sends the analog input data to the UDC
module immediately before it is needed by the UDC module for the next UDC task
scan. The analog input data is stored in UDC register 214/1214. The value may
range from -2047 (-10 volts) to +2047 (+10 volts).