Rainbow Electronics ATmega64L - Manual (Page 98)

98
ATmega16(L)
2466B–09/01
seting (or clearing) the OC1x register at the compare match between OCR1x and
TCNT1, and clearing (or setting) the OC1x register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x register represents special cases when generating a
PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM
(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the
OCR1x equal to TOP will result in a constant high or low output (depending on the polar-
ity of the output set by the COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). The
waveform generated will have a maximum frequency of f
OC 1 A
= f
clk_I/O
/2 when OCR1A is
set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the
double buffer feature of the output compare unit is enabled in the fast PWM mode.
Phase Correct PWM Mode The phase correct pulse width modulation or phase correct PWM mode (WGM13:0 =
1,2,3,10, or 11) provides a high resolution phase correct PWM waveform generation
option. The phase correct PWM mode is, like the phase and frequency correct PWM
mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting compare output
mode, the output compare (OC1x) is cleared on the compare match between TCNT1
and OCR1x while upcounting, and set on the compare match while downcounting. In
inverting output compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the
symmetric feature of the dual-slope PWM modes, these modes are preferred for motor
control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8,9, or 10-bit, or
defined by either ICR1 or OCR1A. The minimum resolution allowed is 2 bit (ICR1 or
OCR1A set to 0x0003), and the maximum resolution is 16 bit (ICR1 or OCR1A set to
MAX). The PWM resolution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches
either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the
value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter
has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM
mode is shown on Figure 47. The figure shows phase correct PWM mode when OCR1A
or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a
histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre-
sent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set
when a compare match occurs.
f
OCn xPW M
f
clk_I/O
N 1 TOP +
( ) ⋅
----------------------------------- =
R
PCPW M
TOP 1 +
( )
log
2
( )
log
----------------------------------- =