Rainbow Electronics ATmega64L - Manual (Page 123)

123
ATmega16(L)
2466B–09/01
.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the
compare match is ignored, but the set or clear is done at TOP. See “Phase Correct
PWM Mode” on page 118 for more details.
• Bit 2:0 - CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
Table 54.
Timer/Counter Register –
TCNT2
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT2 register blocks (removes) the
compare match on the following timer clock. Modifying the counter (TCNT2) while the
counter is running, introduces a risk of missing a compare match between TCNT2 and
the OCR2 register.
Output Compare Register -
OCR2
The Output Compare Register contains an 8-bit value that is continuously compared
with the counter value (TCNT2). A match can be used to generate an output compare
interrupt, or to generate a waveform output on the OC2 pin.
Table 53. Compare Output Mode, Phase Correct PWM Mode (1)
COM21 COM20 Description
0 0 Normal port operation, OC 2 disconnected.
0 1 Reserved
1 0 Clear OC 2 on compare match when up-counting. Set OC2 on compare
match when downcounting.
1 1 Set OC 2 on compare match when up-counting. Clear OC2 on compare
match when downcounting.
Table 54. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/counter stopped)
0 0 1 clk
T2S
/(No prescaling)
0 1 0 clk
T2S
/8 (From prescaler)
0 1 1 clk
T2S
/32 (From prescaler)
1 0 0 clk
T2S
/64 (From prescaler)
1 0 1 clk
T2S
/128 (From prescaler)
1 1 0 clk
T 2 S
/256 (From prescaler)
1 1 1 clk
T 2 S
/1024 (From prescaler)
Bit 7 6 5 4 3 2 1 0
TCNT2[7:0] TCNT2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR2[7:0] OCR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0