Rainbow Electronics ATmega64L - Manual (Page 232)

232
ATmega16(L)
2466B–09/01
If the ADC is not to be used during scan, the recommended input values from Table 91
should be used. The user is recommended not to use the Differential Gain stages dur-
ing scan. Switch-Cap based gain stages require fast operation and accurate timing
which is difficult to obtain when used in a scan chain. Details concerning operations of
the differential gain stage is therefore not provided. For the same reason, the ADC High
Speed Mode (ADHSM) bit does not make any sense during boundary-scan operation.
The AVR ADC is based on the analog circuitry shown in Figure 123 with a successive
approximation algorithm implemented in the digital logic. When used in Boundary-scan,
the problem is usually to ensure that an applied analog voltage is measured within some
limits. This can easily be done without running a successive approximation algorithm:
apply the lower limit on the digital DAC[9:0] lines, make sure the output from the com-
parator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the
output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
When using the ADC, remember the following:
• The Port Pin for the ADC channel in use must be configured to be an input with pull-
up disabled to avoid signal contention.
• In normal mode, a dummy conversion (consisting of 10 comparisons) is performed
when enabling the ADC. The user is advised to wait at least 200 ns after enabling
the ADC before controlling/observing any ADC signal, or perform a dummy
conversion before using the first result.
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD
signal low (Sample mode).
Figure 124 shows the timing diagram for ADC sampling. As long as a static input signal
is measured, the maximum low period of the HOLD signal is not considered. The timing
constraints are given in Table 92. The minimum parameters need normally not be con-
sidered since serial scanning of the Boundary-scan register usually takes considerably
longer time.
Table 92. ADC Timing Constraints
Symbol Parameter Min Max Unit
t
HP
HOLD to PRECH time TBD µs
t
S
PRECH setup time TBD µs
t
H
PRECH hold time TBD µs
t
HOLD
HOLD pulse width TBD µs