Timer/counter 1 – tcnt1h and tcnt1l, Output compare register 1 a – ocr1ah and ocr1al, Output compare register 1 b – ocr1bh and ocr1bl – Rainbow Electronics ATmega64L User Manual
Page 108: Input capture register 1 – icr1h and icr1l, Atmega16(l)
108
ATmega16(L)
2466B–09/01
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will
clock the counter even if the pin is configured as an output. This feature allows software
control of the counting.
Timer/Counter 1 – TCNT1H
and TCNT1L
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit tempo-
rary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 86.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing
a compare match between TCNT1 and one of the OCR1x registers.
Writing to the TCNT1 register blocks (removes) the compare match on the following
timer clock for all compare units.
Output Compare Register 1 A
– OCR1AH and OCR1AL
Output Compare Register 1 B
– OCR1BH and OCR1BL
The output compare registers contain a 16-bit value that is continuously compared with
the counter value (TCNT1). A match can be used to generate an output compare inter-
rupt, or to generate a waveform output on the OC1x pin.
The output compare registers are 16 bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is
performed using an 8-bit temporary high byte register (TEMP). This temporary register
is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 86.
Input Capture Register 1 –
ICR1H and ICR1L
Bit
7
6
5
4
3
2
1
0
TCNT1[15:8]
TCNT1H
TCNT1[7:0]
TCNT1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
OCR1AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0