Rainbow Electronics ATmega64L - Manual (Page 216)

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ATmega16(L)
2466B–09/01
Figure 113. TAP Controller State Diagram
TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the
Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. The
state transitions depicted in Figure 113 depend on the signal present on TMS (shown
adjacent to each state transition) at the time of the rising edge at TCK. The initial state
after a Power-On Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all shift registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG inter-
face is:
• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter
the Shift Instruction Register - Shift-IR state. While in this state, shift the 4 bits of the
JTAG instructions into the JTAG instruction register from the TDI input at the rising
edge of TCK. The TMS input must be held low during input of the 3 LSBs in order to
remain in the Shift-IR state. The MSB of the instruction is shifted in when this state
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
0
1 1 1
0 0
0 0
1 1
1 0
1
1
0
1
0
0
1 0
1
1
0
1
0
0
0 0
1 1