Rainbow Electronics ATmega64L - Manual (Page 105)

105
ATmega16(L)
2466B–09/01
Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the
phase correct or the phase and frequency correct, PWM mode.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is
set. See “Phase Correct PWM Mode” on page 98. for more details.
• Bit 3 - FOC1A: Force Output Compare for Channel A
• Bit 2 - FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to
zero when TCCR1A is written when operating in a PWM mode. When writing a logical
one to the FOC1A/FOC1B bit, an immediate compare match is forced on the waveform
generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits set-
ting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the
value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in clear
timer on compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bit 1:0 - WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
what type of waveform generation to be used, see Table 47. Modes of operation sup-
ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare
match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See
“Modes of Operation” on page 94.)
Table 46. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
(1)
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B
disconnected.
0 1 WGM13 = 0: Normal port operation,
OC1A/OC1B disconnected.
WGM13 = 1: Toggle OC1A on compare match,
OC1B reserved.
1 0 Clear OC1A/OC1B on compare match when
up-counting. Set OC1A/OC1B on compare
match when downcounting.
1 1 Set OC1A/OC1B on compare match when up-
counting. Clear OC1A/OC1B on compare
match when downcounting.