Rainbow Electronics ATmega64L - Manual (Page 15)

15
ATmega16(L)
2466B–09/01
Data Memory Access Times This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
CPU
cycles as described in Figure
10.
Figure 10. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address Address Valid
T1 T2 T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction Next Instruction