Rainbow Electronics ATmega64L - Manual (Page 149)

149
ATmega16(L)
2466B–09/01
The PE bit is set if the next character that can be read from the receive buffer had a par-
ity error when received and the parity checking was enabled at that point (UPM1 = 1).
This bit is valid until the receive buffer (UDR) is read.
Disabling the Receiver In contrast to the transmitter, disabling of the receiver will be immediate. Data from
ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero)
the receiver will no longer override the normal function of the RxD port pin. The receiver
buffer FIFO will be flushed when the receiver is disabled. Remaining data in the buffer
will be lost
Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the receiver is disabled, i.e., the buffer will
be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during
normal operation, due to for instance an error condition, read the UDR I/O location until
the RXC flag is cleared. The following code example shows how to flush the receive
buffer.
Note: 1. The example code assumes that the part specific header file is included.
Assembly Code Example (1)
USART_Flush:
sbis UCSRA, RXC
ret
in r16, UDR
rjmp USART_Flush
C Code Example (1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRA & (1<
}