Rainbow Electronics ATA5812 - Manual (Page 54)

54
ATA5811/ATA5812 [Preliminary]
4689B–RKE–04/04
Figure 45. Timing Diagram for Failed Bit-check (Condition CV_Lim < Lim_min)
Figure 46. Timing Diagram for Failed Bit-check (Condition: CV_Lim
≥
Lim_max)
Duration of the Bit-check If no transmitter is present during the Bit-check, the output of the ASK/FSK demodulator
delivers random signals. The Bit-check is a statistical process and T
Bit-check
varies for
each check. Therefore, an average value for T
Bit-check
is given in the electrical character-
istics. T
Bit-check
depends on the selected baud rate range and on T
XDCLK
. A higher baud-
rate range causes a lower value for T
Bit-check
resulting in a lower current consumption in
RX polling mode.
RX_ACTIVE
Bit check
Demod_Out
Bit-check counter 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112 0 0
(Lim_min = 14, Lim_max = 24)
T
Startup_Sig_Proc
1/2 Bit
Bit check failed (CV_Lim < Lim_min)
T
Bit-check
Start-up mode Bit-check mode
T
Sleep
Sleep mode
RX_ACTIVE
Bit check
Demod_Out
Bit-check counter 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112 0 0
(Lim_min = 14, Lim_max = 24)
T
Startup_Sig_Proc
1/2 Bit
Bit check failed (CV_Lim >= Lim_min)
T
Bit-check
Start-up mode Bit-check mode
T
Sleep
Sleep mode
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