Rainbow Electronics ATA5812 - Manual (Page 40)

40
ATA5811/ATA5812 [Preliminary]
4689B–RKE–04/04
Pin Tn To switch the transceiver from OFF to Idle mode, pin Tn must set to 0 (maximum
0.2
×
V
VS2
) for at least T
Tn_IRQ
(see Figure 28). The transceiver recognize the negative
edge, sets pin N_RESET to low and switches on DVCC, AVCC and the power supply for
external devices VSOUT.
If V
DVCC
exceeds 1.5 V (typically) and the XTO is settled, the digital control logic is active
and sets the status bit STn to 1 and an interrupt is issued (T
Tn_IRQ
).
After the voltage on pin VSOUT exceeds 2.3 V (typically) and the start-up time of the
XTO is elapsed the output clock on pin CLK is available. Because the enabling of pin
CLK is asynchronous the first clock cycle may be incomplete. N_RESET is set to high if
V
VSOUT
exceeds 2.38 V (typically) and the XTO is settled.
Figure 28. Timing Pin Tn, Status Bit STn
VSOUT
Tn
N_RESET
IRQ
STn
(Status Register)
CLK
OFF
Mode
IDLE
Mode
DVCC, AVCC
T
Tn_IRQ
1.5 V (typ)
V
Thres_1
= 2.3 V (typ)
V
Thres_2
= 2.38 V (typ)