Rainbow Electronics ATA5812 - Manual (Page 53)

53
ATA5811/ATA5812 [Preliminary]
4689B–RKE–04/04
For the best noise immunity it is recommended to use a low span between T
Lim_min
and
T
Lim_max
. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter
preburst. A '11111...' or a '10101...' sequence in Manchester or Bi-phase is a good
choice concerning that advice. A good compromise between sensitivity and susceptibil-
ity to noise regarding the expected edge to edge time t
ee
is a time window of ±38%, to
get the maximum sensitivity the time window should be ±50% and then N
Bit-check
≥
6.
Using preburst patterns that contain various edge to edge time periods, the Bit-check
limits must be programmed according to the required span.
The Bit-check limits are determined by means of the formula below:
T
Lim_min
= Lim_min
×
T
XDCLK
T
Lim_max
= (Lim_max - 1)
×
T
XDCLK
Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.
Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.
Using the above formulas, Lim_min and Lim_max can be determined according to the
required T
Lim_min
, T
Lim_max
and T
XDCLK
. The time resolution defining T
Lim_min
and T
Lim_max
is T
XDCLK
. The minimum edge to edge time t
ee
is defined according to the section
“Receiving Mode”. The lower limit should be set to Lim_min
≥
10. The maximum value of
the upper limit is Lim_max = 63.
Figure 44, Figure 45 on page 54, and Figure 46 on page 54 illustrate the Bit-check for
the Bit-check limits Lim_min = 14 and Lim_max = 24. The signal processing circuits are
enabled during T
Startup_PLL
and T
Startup_Sig_Proc
. The output of the ASK/FSK demodulator
(Demod_Out) is undefined during that period. When the Bit-check becomes active, the
Bit-check counter is clocked with the cycle T
XDCLK
.
Figure 44 shows how the Bit-check proceeds if the Bit-check counter value CV_Lim is
within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
Figure 45 on page 54 the Bit-check fails as the value CV_Lim is lower than the limit
Lim_min. The Bit-check also fails if CV_Lim reaches Lim_max. This is illustrated in Fig-
ure 46 on page 54.
Figure 44. Timing Diagram During Bit-check
RX_ACTIVE
Bit check
Demod_Out
Bit-check counter
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 11 0 12131415 1 2 3 4
(Lim_min = 14, Lim_max = 24)
T
Startup_Sig_Proc
1/2 Bit 1/2 Bit 1/2 Bit
Bit check ok Bit check ok
5 6 7
T
Bit-check
Start-up mode Bit-check mode
T
XDCLK