Rainbow Electronics ATA5812 - Manual (Page 49)

49
ATA5811/ATA5812 [Preliminary]
4689B–RKE–04/04
To save current it is recommended CLK and V
VSOUT
be disabled during RX polling
mode. I
P
does not include the current of the Microcontroller_Interface I
VSINT
and the cur-
rent of an external device connected to pin VSOUT (e.g., microcontroller). If CLK
and/or VSOUT is enabled during RX polling mode the current consumption is calculated
as follows:
During T
Sleep
, T
Startup_PLL
and T
Startup_Sig_Proc
the transceiver is not sensitive to a transmit-
ter signal. To guarantee the reception of a transmitted command the transmitter
must start the telegram with an adequate preburst. The required length of the
preburst T
Preburst
depends on the polling parameters T
Sleep
, T
Startup_PLL
, T
Startup_Sig_Proc
and T
Bit-check
. Thus, T
Bit-check
depends on the actual bit rate and the number of bits
(N
Bit-check
) to be tested
.
Sleep Mode The length of period T
Sleep
is defined by the 5-bit word sleep in control register 4, the
extension factor X
Sleep
defined by the bit XSleep in control register 4 and the basic clock
cycle T
DCLK
. It is calculated to be:
In US and European applications, the maximum value of T
Sleep
is about 38 ms if X
Sleep
is
set to 1 (which is done by setting the bit XSleep in control register 4 to 0). The time res-
olution is about 1.2 ms in that case. The sleep time can be extended to about 300 ms by
setting X
Sleep
to 8 (which is done by setting XSleep in control register 4 to 1), the time
resolution is then about 9.6 ms.
Start-up Mode During T
Startup_PLL
the PLL is enabled and starts up. If the PLL is locked, the signal pro-
cessing circuit starts up (T
Startup_Sig_Proc
). After the start-up time all circuits are in stable
condition and ready to receive.
I
S_Poll
I
P
I
VSINT
I
EXT
+ + =
T
Preburst
T
Sleep
T
Startup_PLL
T
Startup_Sig_Proc
T
Bit_check
+ + +
≥
T
Sleep
Sleep 1024 T
DCLK
X
Sleep
Ч Ч Ч
=