Rainbow Electronics ATA5812 - Manual (Page 29)

29
ATA5811/ATA5812 [Preliminary]
4689B–RKE–04/04
AUX Mode The transceiver changes from OFF mode to AUX mode if the voltage at pin VAUX
V
VAUX
> 3.5 V (typically). In AUX mode DVCC and VSOUT are connected to the auxil-
iary power supply input (VAUX) via the voltage regulator V_REG2. In AUX mode the
transceiver is programmable via the 4-wire serial interface, but no RX or TX operations
are possible because AVCC = OFF.
The state transition OFF mode to AUX mode is indicated by an interrupt at pin IRQ and
the status bit P_On_Aux = 1.
Idle Mode In Idle mode AVCC and DVCC are connected to the battery voltage (VS1).
From OFF mode the transceiver changes to Idle mode if pin PWR_ON is set to 1 or pin
T1, T2, T3, T4 or T5 is set to 0. This state transition is indicated by an interrupt at pin
IRQ and the status bits Power_On = 1 or ST1, ST2, ST3, ST4 or ST5 = 1.
From AUX mode the transceiver changes to Idle mode by setting AVCC_EN = 1 in con-
trol register 1 via the 4-wire serial interface or if pin PWR_ON is set to 1 or pin T1, T2,
T3, T4 or T5 is set to 0.
VSOUT is either connected to VS1 or to the auxiliary power supply (V_REG2).
If V
VAUX
< VS1 + 0.5 V, VSOUT is connected to VS1. If V
VAUX
> V
S1
+ 0.5 V, VSOUT is
connected to V_REG2 and the status bit P_On_Aux is set to 1.
In Idle mode the RF transceiver is disabled and the power consumption I
S_IDLE
is about
230 µA (VSOUT OFF and CLK output OFF VS1 = VS2 = 3 V). The exact value of this
current is strongly dependent on the application and the exact operation mode, there-
fore check the section “Electrical Characteristics” for the appropriate application case.
Via the 4-wire serial interface a connected microcontroller can program the required
parameter and enable the TX, RX polling or RX mode.
The transceiver can be set back to OFF mode by an OFF command via the 4-wire serial
interface (the bit AVCC_EN must be set to 0, the input level of pin PWR_ON must be 0
and pin T1, T2, T3, T4 and T5 = 1 before writing the OFF command).
Reset Timing and Reset
Logic If the transceiver is switched on (OFF mode to Idle mode, OFF mode to AUX mode)
DVCC and VSOUT are ramping up as illustrated in Figure 23 on page 30 (AVCC only
ramps up if the transceiver is set to the Idle mode). The internal signal DVCC_RESET
resets the digital control logic and sets the control register to default values.
A voltage monitor generates a low level at pin N_RESET until the voltage at pin VSOUT
exceeds 2.38 V (typically) and the start-up time of the XTO has elapsed (amplitude
detector, see Figure 19 on page 24). After the voltage at pin VSOUT exceeds 2.3 V (typ-
ically) and the start-up time of the XTO has elapsed the output clock at pin CLK is
available. Because the enabling of pin CLK is asynchronous the first clock cycle may be
incomplete.
The status bit Low_Batt is set to 1 if the voltage at pin VSOUT V
VSOUT
drops below
V
Thres_2
(typically 2.38 V). Low_Batt is set to 0 if V
VSOUT
exceeds V
Thres_2
and the status
register is read via the 4-wire serial interface or N_RESET is set to low.
Table 13. Control Register 1
OPM1 OPM0 Function
0 0 Idle mode