Rainbow Electronics 71M6542G - Manual (Page 88)

88 © 2008–2011 Teridian Semiconductor Corporation v1.1
Wake Enable Wake Flag
De-bounce Description
Name Location Name Location
bounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Always Enabled WF_RST 28B0[6] 2 µs Wake after RESET.
Always Enabled WF_RSTBIT 28B0[5] No Wake after RESET bit.
Always Enabled WF_ERST 28B0[3] 2 µs
Wake after E_RST.
(ICE must be enabled)
Always Enabled WF_OVF 28B0[4] No Wake after WD reset.
Always Enabled WF_CSTART 28B0[7] No
Wake after cold start - the first
application of power.
Always Enabled WF_BADVDD 28B0[2] No
Wake after insufficient VBAT
voltage.
† 71M6542F only.
*This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This
pin is high-level sensitive.