Rainbow Electronics T89C51CC02 - Manual (Page 91)

Rev.A - May 17, 2001 91
Preliminary
T89C51CC02
CANSTCH (S:B2h)
CAN message object Status Register
NOTE:
See Figure 59.
No default value after reset.
Figure 79. CANSTCH Register
7 6 5 4 3 2 1 0
DLCW TXOK RXOK BERR SERR CERR FERR AERR
Bit Number Bit Mnemonic Description
7 DLCW
Data length code warning
The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of
the CANCONCH register is updated by the received DLC.
6 TXOK
Transmit OK
The communication enabled by transmission is completed.
When the controller is ready to send a frame, if two or more message objects are enabled as producers,
the lower index message object (0 to 13) is supplied first.
This flag can generate an interrupt.
5 RXOK
Receive OK
The communication enabled by reception is completed.
In the case of two or more message object reception hits, the lower index message object (0 to 13)
is updated first.
This flag can generate an interrupt.
4 BERR
Bit error (only in transmission)
The bit value monitored is different from the bit value sent.
Exceptions:
the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge
slot detecting a dominant bit during the sending of an error frame.
This flag can generate an interrupt.
3 SERR
Stuff error
Detection of more than five consecutive bits with the same polarity.
This flag can generate an interrupt.
2 CERR
CRC error
The receiver performs a CRC check on each destuffed received message from the start of frame up
to the data field.
If this checking does not match with the destuffed CRC field, a CRC error is set.
This flag can generate an interrupt.
1 FERR
Form error
The form error results from one or more violations of the fixed form in the following bit fields:
CRC delimiter
acknowledgment delimiter
end_of_frame
This flag can generate an interrupt.
0 AERR
Acknowledgment error
No detection of the dominant bit in the acknowledge slot.
This flag can generate an interrupt.