Rainbow Electronics T89C51CC02 - Manual (Page 116)

116 Rev.A - May 17, 2001
Preliminary
T89C51CC02
17.4. ADC Converter Operation
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
The busy flag ADSST(ADCON.3) is automatically set when an A/D conversion is running. After completion of
the A/D conversion, it is cleared by hardware. This flag can be read only, a write has no effect.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and
ADDL, it is cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set
(see Figure 120). Clear this flag for re-arming the interrupt.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection.
Before Starting Power reduction modes the ADC conversion has to be completed.
Table 22. Selected Analog input
17.5. Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage
equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line
linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range!
SCH2 SCH1 SCH0 Selected Analog input
0 0 0 AN0
0 0 1 AN1
0 1 0 AN2
0 1 1 AN3
1 0 0 AN4
1 0 1 AN5
1 1 0 AN6
1 1 1 AN7