Rainbow Electronics T89C51CC02 - Manual (Page 13)

Rev.A - May 17, 2001 13
Preliminary
T89C51CC02
6. Clock
6.1. Introduction
The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the
following advantages:
•
Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.
•
Saves power consumption while keeping the same CPU power (oscillator power saving).
•
Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.
•
Increases CPU power by 2 while keeping the same crystal frequency.
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by the software.
An extra feature is available for selected hardware in the X2 mode. This feature allows starting of the CPU in the
X2 mode, without starting in the standard mode.
The hardware CPU X2 mode can be read and write via IAP (SetX2mode, ClearX2mode, ReadX2mode), see In-
System Programming section.
These IAPs are detailed in the "In-System Programming" section.
6.2. Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 3. shows the clock generation
block diagram. The X2 bit is validated on the XTAL1
÷
2 rising edge to avoid glitches when switching from the
X2 to the STD mode. Figure 4 shows the mode switching waveforms.