Rainbow Electronics ATmega8515L - Manual (Page 39)

39
ATmega8515(L)
2512A–AVR–04/02
• Bits 7 – SM0: Sleep Mode Select Bit 0
The Sleep Mode Select bits select between the three available sleep modes as shown
in Table 16.
Note: 1. Standby mode is only available with external crystals or resonators.
Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter
Idle m ode, stopping the CPU but all owing SPI, USART, Anal og Com parator,
Timer/Counters, Watchdog, and the Interrupt System to continue operating. This sleep
mode basically halts clk
CPU
and clk
FLASH
, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-
tus Register – ACSR. This will reduce power consumption in Idle mode.
Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the External
Interrupts and the Watchdog continue operating (if enabled). Only an External Reset, a
Watchdog Reset, a Brown-out Reset, an External level interrupt on INT0 or INT1, or an
External interrupt on INT2 can wake up the MCU. This sleep mode basically halts all
generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Inter-
rupts” on page 74 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as described in “Clock Sources” on page
32.
Table 16. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
0 0 0 Idle
0 0 1 Reserved
0 1 0 Power-down
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Standby (1)
1 1 1 Reserved