Rainbow Electronics ATmega8515L - Manual (Page 203)

203
ATmega8515(L)
2512A–AVR–04/02
Figure 91. External Memory Timing (SRWn1 = 1, SRWn0 = 0)
Figure 92. External Memory Timing (SRWn1 = 1, SRWn0 = 1)
(1)
Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction
accesses the RAM (internal or external).
ALE
T1 T2 T3
Wr
ite
Read
WR
T6
A15:8 Address Prev. Addr.
DA7:0 Address Data Prev. Data XX
RD
DA7:0 (XMBK = 0) Data Address
System Clock (CLK CPU )
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4 T5
ALE
T1 T2 T3
Wr
ite
Read
WR
T7
A15:8 Address Prev. Addr.
DA7:0 Address Data Prev. Data XX
RD
DA7:0 (XMBK = 0) Data Address
System Clock (CLK CPU )
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4 T5 T6