Address latch requirements, Pull-up and bus keeper, Timing – Rainbow Electronics ATmega8515L User Manual
Page 24: Atmega8515(l), Sram
24
ATmega8515(L)
2512A–AVR–04/02
data direction settings are used. Note that when the XMEM interface is disabled, the
address space above the internal SRAM boundary is not mapped into the internal
SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal
latch (typically “74x573” or equivalent) which is transparent when G is high.
Address Latch Requirements
Due to the high-speed operation of the XRAM interface, the address latch must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style 74HC series
latch becomes inadequate. The external memory interface is designed in compliance to
the 74AHC series latch. However, most latches can be used as long they comply with
the main timing parameters. The main parameters for the address latch are:
•
D to Q propagation delay (t
pd
)
•
Data setup time before G low (t
su
)
•
Data (address) hold time after G low (
th
)
The external memory interface is designed to guaranty minimum address hold time after
G is asserted low of t
h
= 5 ns (refer to t
LAXX_LD
/t
LLAXX_ST
in Table 99 to Table 106 on page
201). The D to Q propagation delay (t
pd
) must be taken into consideration when calculat-
ing the access time requirement of the external component. The data setup time before
G low (t
su
) must not exceed address valid to ALE low (t
AVLLC
) minus PCB wiring delay
(dependent on the capacitive load).
Figure 12. External SRAM Connected to the AVR
Pull-up and Bus Keeper
The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port reg-
ister is written to one. To reduce power consumption in sleep mode, it is recommended
to disable the pull-ups by writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus keeper on the AD7:0 lines. The bus keeper
can be disabled and enabled in software as described in “Special Function IO Register –
SFIOR” on page 29. When enabled, the bus keeper will keep the previous value on the
AD7:0 bus while these lines are tri-stated by the XMEM interface.
If neither bus-keeper nor pull-ups are enabled, the XMEM interface will leave the AD7:0
tri-stated during a read access until the next RAM access (internal or external) appears.
Timing
External memory devices have various timing requirements. To meet these require-
ments, the ATmega8515 XMEM interface provides four different wait states as shown in
Table 3. It is important to consider the timing specification of the external memory
device before selecting the wait state. The most important parameters are the access
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
D
Q
G
AD7:0
ALE
A15:8
RD
WR
AVR