External data memory timing, Table 99, Atmega8515(l) – Rainbow Electronics ATmega8515L User Manual
Page 199
199
ATmega8515(L)
2512A–AVR–04/02
External Data Memory Timing
Notes:
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 99. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
Symbol
Parameter
8 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
0
1/t
CLCL
Oscillator Frequency
0.0
16
MHz
1
t
LHLL
ALE Pulse Width
115
1.0t
CLCL
-10
ns
2
t
AVLL
Address Valid A to ALE Low
57.5
0.5t
CLCL
-5
ns
3a
t
LLAX_ST
Address Hold After ALE Low,
write access
5
5
ns
3b
t
LLAX_LD
Address Hold after ALE Low,
read access
5
5
ns
4
t
AVLLC
Address Valid C to ALE Low
57.5
0.5t
CLCL
-5
ns
5
t
AVRL
Address Valid to RD Low
115
1.0t
CLCL
-10
ns
6
t
AVWL
Address Valid to WR Low
115
1.0t
CLCL
-10
ns
7
t
LLWL
ALE Low to WR Low
47.5
67.5
0.5t
CLCL
-15
0.5t
CLCL
+5
ns
8
t
LLRL
ALE Low to RD Low
47.5
67.5
0.5t
CLCL
-15
0.5t
CLCL
+5
ns
9
t
DVRH
Data Setup to RD High
40
40
ns
10
t
RLDV
Read Low to Data Valid
75
1.0t
CLCL
-50
ns
11
t
RHDX
Data Hold After RD High
0
0
ns
12
t
RLRH
RD Pulse Width
115
1.0t
CLCL
-10
ns
13
t
DVWL
Data Setup to WR Low
42.5
0.5t
CLCL
-20
ns
14
t
WHDX
Data Hold After WR High
115
1.0t
CLCL
-10
ns
15
t
DVWH
Data Valid to WR High
125
1.0t
CLCL
ns
16
t
WLWH
WR Pulse Width
115
1.0t
CLCL
-10
ns
Table 100. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state
Symbol
Parameter
8 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
0
1/t
CLCL
Oscillator Frequency
0.0
16
MHz
10
t
RLDV
Read Low to Data Valid
200
2.0t
CLCL
-50
ns
12
t
RLRH
RD Pulse Width
240
2.0t
CLCL
-10
ns
15
t
DVWH
Data Valid to WR High
240
2.0t
CLCL
ns
16
t
WLWH
WR Pulse Width
240
2.0t
CLCL
-10
ns