Rainbow Electronics ATmega8515L - Manual (Page 202)

202
ATmega8515(L)
2512A–AVR–04/02
Figure 89. External Memory Timing (SRWn1 = 0, SRWn0 = 0
Figure 90. External Memory Timing (SRWn1 = 0, SRWn0 = 1)
ALE
T1 T2 T3
Wr
ite
Read
WR
T4
A15:8 Address Prev. Addr.
DA7:0 Address Data Prev. Data XX
RD
DA7:0 (XMBK = 0) Data Address
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
ALE
T1 T2 T3
Wr
ite
Read
WR
T5
A15:8 Address Prev. Addr.
DA7:0 Address Data Prev. Data XX
RD
DA7:0 (XMBK = 0) Data Address
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4