Rainbow Electronics ATmega8515L - Manual (Page 121)

121
ATmega8515(L)
2512A–AVR–04/02
• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 51) is executed when the
OCF1A flag, located in TIFR, is set.
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 51) is executed when the
OCF1B flag, located in TIFR, is set.
• Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
b al l y e na bl ed ), th e Ti m e r/Co u nte r1 in pu t ca ptu re in te rru pt i s e na bl e d. T h e
corresponding Interrupt Vector (see “Interrupts” on page 51) is executed when the ICF1
flag, located in TIFR, is set.
Timer/Counter Interrupt Flag
Register – TIFR
(1)
Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are
described in this section. The remaining bits are described in their respective timer
sections.
• Bit 7 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC
modes, the TOV1 flag is set when the timer overflows. Refer to Table 53 on page 118
for the TOV1 flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is
executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
• Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output compare Match A Interrupt Vector is
executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output compare Match B Interrupt vector is
executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
Bit 7 6 5 4 3 2 1 0
TOV1 OCF1A OC1FB – ICF1 – TOV0 OCF0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0