Rainbow Electronics ATmega8515L - Manual (Page 25)

25
ATmega8515(L)
2512A–AVR–04/02
time for the external memory in conjunction with the set-up requirement of the
ATmega8515. The access time for the external memory is defined to be the time from
receiving the chip select/address until the data of this address actually is driven on the
bus. The access time cannot exceed the time from the ALE pulse is asserted low until
data must be stable during a read sequence (t
LLRL
+ t
RLRH
- t
DVRH
in Table 99 to Table
106 on page 201). The different wait states are set up in software. As an additional fea-
ture, it is possible to divide the external memory space in two sectors with individual wait
state settings. This makes it possible to connect two different memory devices with dif-
ferent timing requirements to the same XMEM interface. For XMEM interface timing
details, please refer to Figure 89 to Figure 92, and Table 99 to Table 106.
Note that the XMEM interface is asynchronous and that the waveforms in the figures
below are related to the internal system clock. The skew between the Internal and Exter-
nal clock (XTAL1) is not guaranteed (it varies between devices, temperature, and supply
voltage). Consequently, the XMEM interface is not suited for synchronous operation.
Figure 13. External Data Memor y Cycles without Wait State (SRWn1 = 0 and
SRWn0 = 0)
(1)
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector)
The ALE pulse in period T4 is only present if the next instruction accesses the RAM
(internal or external).
ALE
T1 T2 T3
Wr
ite
Read
WR
T4
A15:8 Address Prev. Addr.
DA7:0 Address Data Prev. Data XX
RD
DA7:0 (XMBK = 0) Data Prev. Data Address
Data Prev. Data Address DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)