Rainbow Electronics ATmega8515L - Manual (Page 114)

114
ATmega8515(L)
2512A–AVR–04/02
Timer/Counter Timing
Diagrams The Timer/Counter is a synchronous design and the timer clock (clk
T1
) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when interrupt flags are set, and when the OCR1x Register is updated with the
OCR1x buffer value (only for modes utilizing double buffering). Figure 55 shows a timing
diagram for the setting of OCF1x.
Figure 55. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 56 shows the same timing data, but with the prescaler enabled.
Figure 56. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
clk_I/O
/8)
Figure 57 shows the count sequence close to TOP in various modes. When using phase
and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The
timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at
BOTTOM.
clk
Tn
(clk
I/O
/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)