Rainbow Electronics ATmega8515L - Manual (Page 22)

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ATmega8515(L)
2512A–AVR–04/02
I/O Memory The I/O space definition of the ATmega8515 is shown in “Register Summary” on page
209.
All ATmega8515 I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions, transferring data between the 32 general pur-
pose working registers and the I/O space. I/O Registers within the address range $00 -
$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as
data space using LD and ST instructions, $20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a one back into
any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-
isters $00 to $1F only.
The I/O and peripherals control registers are explained in later sections.
External Memory
Interface With all the features the External Memory Interface provides, it is well suited to operate
as an interface to memory devices such as external SRAM and Flash, and peripherals
such as LCD-display, A/D, and D/A. The main features are:
•
Four Different Wait State Settings (Including No wait State)
• Independent Wait State Setting for Different External Memory Sectors (Configurable
Sector Size)
• The Number of Bits Dedicated to Address High Byte is Selectable
• Bus Keepers on Data Lines to Minimize Current Consumption (Optional)
Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal
SRAM becomes available using the dedicated external memory pins (see Figure 1 on
page 2, Table 26 on page 63, Table 32 on page 67, and Table 38 on page 71). The
memory configuration is shown in Figure 11.