Initialization requirements 6, 1 power management, hot-swap, and reset signals, Initialization requirements – Intel 21555 User Manual
Page 65: Power management, hot-swap, and reset signals, Chapter 6, “initialization requirements
21555 Non-Transparent PCI-to-PCI Bridge User Manual
65
Initialization Requirements
6
This chapter presents the theory of operation information about the 21555 initialization requirements. See
for specific information about the initialization registers.
6.1
Power Management, Hot-Swap, and Reset Signals
describes the power management, hot-swap, and reset signals.
Table 17. Power Management, Hot-Swap, and Reset Signals (Sheet 1 of 2)
Signal Name
Type
Description
l_stat
TS
CompactPCI hot-swap local status pin. As an input to the 21555, this signal indicates
the sense of the ejector switch and therefore the state of the LED in a CompactPCI
card supporting distributed hot-swap. As an output from the 21555, it controls the LED.
When CompactPCI hot-swap is not supported by the add-in card, this signal should be
tied low with a 1k resistor.
p_enum_l
OD
Primary bus CompactPCI hot-swap event. Conditionally asserted by the 21555, this
signal indicates either that the card has been inserted and is ready for configuration, or
that the card is about to be removed. This signal is deasserted when the
corresponding insertion or removal event bit is cleared.
This signal should be pulled up by an external resistor.
p_pme_l
OD
Primary bus power management event. Provides power management signaling
capability on behalf of the subsystem. The 21555 asserts p_pme_l when all of the
following are true:
•
Signal s_pme_l is asserted low.
•
Signal p_pme_l is supported in the current power state.
•
PME_EN bit is set. (See
Table 120, “Power Management Control and Status
.)
Once asserted, p_pme_l is deasserted when the PME status bit or the PME_EN bit is
cleared. If the PME# isolation circuitry is needed, it must be implemented externally.
p_rst_l
I
Primary PCI bus RST#. Signal p_rst_l forces the 21555 to a known state. All register
state is cleared, and all PCI bus outputs are tristated, with the exception of s_ad,
s_cbe_l, and s_par if the 21555 is designated as the central function.
Tristated signals are:
•
p_perr_l
•
p_serr_l
•
p_inta_l
•
p_enum_l
•
p_pme_l
•
p_req_l
•
s_perr_l
•
s_serr_l
•
s_inta_l
•
s_gnt_l [8:0].
Signal p_rst_l is asynchronous to p_clk.