Intel 21555 User Manual

Intel Hardware

21555 Non-Transparent PCI-to-
PCI Bridge

User Manual

July 2001

Order Number: 278321–002

Table of contents

Document Outline

21555 Non-Transparent PCI-to- PCI Bridge
Copyright
Contents
Preface 1
- 1.1 Cautions and Notes
- 1.2 Data Units
- 1.3 Numbering
- 1.4 Signal Nomenclature
- 1.5 Register Abbreviations
Introduction 2
- 2.1 Comparing a 21555 to a Transparent PPB
- 2.2 Architectural Overview
- 2.3 Special Applications
  - 2.3.1 Primary Bus VGA Support
  - 2.3.2 Secondary Bus VGA Support
- 2.4 Programming Notes
Signal Descriptions 3
- 3.1 Primary PCI Bus Interface Signals
- 3.2 Primary PCI Bus Interface 64Bit Extension Signals
- 3.3 Secondary PCI Bus Interface Signals
- 3.4 Secondary PCI Bus Interface 64Bit Extension Signals
- 3.5 Miscellaneous Signals
Address Decoding 4
- 4.1 CSR Address Decoding
- 4.2 Expansion ROM Address Mapping (Decoding)
- 4.3 Memory 0 Transaction Address Decoding
- 4.4 I/O Transaction Address Decoding
  - 4.4.1 Indirect I/O Transaction Generation
  - 4.4.2 Subtractive Decoding of I/O Transactions
- 4.5 Configuration Accesses
  - 4.5.1 Type 0 Accesses to 21555 Configuration Space
  - 4.5.2 Initiation of Configuration Transactions by 21555
- 4.6 21555 Bar Summary
PCI Bus Transactions 5
- 5.1 Transactions Overview
- 5.2 Posted Write Transactions
- 5.3 Delayed Write Transactions
- 5.4 Delayed Read Transactions
- 5.5 64Bit and 32Bit Transactions Initiated by the 21555
- 5.6 Target Terminations
  - 5.6.1 Target Terminations Returned by the 21555
  - 5.6.2 Transaction Termination Errors on the Target Bus
- 5.7 Ordering Rules
Initialization Requirements 6
- 6.1 Power Management, Hot-Swap, and Reset Signals
- 6.2 Reset Behavior
  - 6.2.1 Central Function During Reset
- 6.3 21555 Initialization
- 6.4 Power Management Support
- 6.5 CompactPCI HotSwap Functionality
  - 6.5.1 Overview of CompactPCI Controller Hardware Interface
  - 6.5.2 Insertion and Removal Process
Clocking 7
- 7.1 Primary and Secondary PCI Bus Clock Signals
- 7.2 21555 Secondary Clock Outputs
- 7.3 66 MHz Support
Parallel ROM Interface 8
- 8.1 Interface Signals
- 8.2 Parallel and Serial ROM Connection
- 8.3 PROM Read by CSR Access
- 8.4 PROM Write by CSR Access
- 8.5 PROM Dword Read
- 8.6 Access Time and Strobe Control
- 8.7 Attaching Additional Devices to the ROM Interface
Serial ROM Interface 9
- 9.1 SROM Interface Signals
- 9.2 SROMSROM Preload Operation
- 9.3 SROM Configuration Data Preload Format
- 9.4 SROM Operation by CSR Access
Arbitration 10
- 10.1 Primary PCI Bus Arbitration Signals
- 10.2 Secondary PCI Bus Arbitration Signals
- 10.3 Primary PCI Bus Arbitration
- 10.4 Secondary PCI Bus Arbitration
  - 10.4.1 Secondary Bus Arbitration Using the Internal Arbiter
  - 10.4.2 Secondary Bus Arbitration Using an External Arbiter
Interrupt and Scratchpad Registers 11
- 11.1 Primary and Secondary PCI Bus Interrupt Signals
- 11.2 Interrupt Support
- 11.3 Doorbell Interrupts
- 11.4 Scratchpad Registers
Error Handling 12
- 12.1 Error Signals
  - 12.1.1 Primary PCI Bus Error Signals
  - 12.1.2 Secondary PCI Bus Error Signals
- 12.2 Parity Errors
- 12.3 System Error (SERR#) Reporting
JTAG Test Port 13
- 13.1 JTAG Signals
- 13.2 Test Access Port Controller
  - 13.2.1 Initialization
I2O Support 14
- 14.1 Inbound Message Passing
- 14.2 Outbound Message Passing
- 14.3 Notes
VPD Support 15
- 15.1 Reading VPD Information
- 15.2 Writing VPD Information
List of Registers 16
- 16.1 Register Summary
- 16.2 Configuration Registers
- 16.3 Control and Status Registers
- 16.4 Address Decoding
  - 16.4.1 Primary and Secondary Address
  - 16.4.2 Configuration Transaction Generation Registers
- 16.5 PCI Registers
- 16.6 I2O Registers
- 16.7 Interrupt Registers
- 16.8 Scratchpad Registers
- 16.9 PROM Registers
- 16.10 SROM Registers
- 16.11 Arbiter Control
- 16.12 Error Registers
- 16.13 Init Registers
- 16.14 JTAG Registers
- 16.15 VPD Registers
Acronyms A
Index