Pci bus transactions 5, 1 transactions overview, Pci bus transactions – Intel 21555 User Manual
Page 49: Transactions overview, Chapter 5, “pci bus transactions
21555 Non-Transparent PCI-to-PCI Bridge User Manual
49
PCI Bus Transactions
5
This chapter presents the theory of operation information about PCI transactions. See
for specific
information about PCI registers. The following sections are discussed:
•
Section 5.2, “Posted Write Transactions” on page 50
.
•
Section 5.3, “Delayed Write Transactions” on page 54
•
Section 5.4, “Delayed Read Transactions” on page 55
•
Section 5.5, “64-Bit and 32-Bit Transactions Initiated by the 21555” on page 59
•
Section 5.6, “Target Terminations” on page 60
•
Section 5.7, “Ordering Rules” on page 61
5.1
Transactions Overview
The 21555 responds to transactions using these commands as a target on both interfaces. The 21555 does not
respond to transactions using any other PCI commands.
•
All memory commands.
•
Dual-address commands.
•
I/O read and write commands.
•
Type 0 configuration commands.
The 21555 can initiate transactions using the Type 0 and Type 1configuration commands on either interface.
The 21555:
•
Responds to transactions by asserting DEVSEL# with medium timing.
•
Can subtractively decode I/O transactions in the primary direction only.
•
Supports linear increment address mode only and disconnects memory transactions whose low two address bits
are not 00b after a single Dword.