Index – Intel 21555 User Manual
Page 197
21555 Non-Transparent PCI-to-PCI Bridge User Manual
197
Index
3-V 15
5-V 15
Primary lockout bit
on the PROM_AD 82
A
Add-in card vendors 15
address 33
Address range locations
Primary BARs 33
Secondary BARs 33
Address space 34
64-bit 35
expansion ROM decoding 34
type of 130, 132
type of for secondary 131
Address translation 33, 36
Addressing model
About the flat 16
B
BAR
and Memory 0 34
Byte offsets 121
C
Cache line
definition of 50
primary and secondary signals 77
CLS
about 50
Configuration register summary 122
CSR
address decoding 34
summary 126
D
delayed 43
Delayed read transactions 55
Delayed transaction
17
data buffers 18
I/O 43
queues 44
subtractive decoding 44
target retry counter 45
Delayed write transactions 54
Device ID 122
Domains
processor 15
Doorbell interrupt functionality 103
F
Fast Back-to-Back 52
Features
of the 21555 15
Flat addressing model 16
I
I2O
capable system 15
Inbound message passing 113
IOP
definition of 15
M
Memory 36
Memory 0 35, 36, 42, 47, 130, 133, 137
about 34
N
Nonprefetchable reads 56
Nontransparent versus transparent
overview of 15
O
Other transparent device 15
Outboard message passing 115
P
PCI bus description
Nonprefetchable reads 56
PCI bus transactions 49
PCI universal card edge connector 15
Posted write queue tuning 53
Posted write transactions 50
PPB
definition of 15
Prefetchable reads 57
Primary 69, 70, 82
Primary Lockout Bit
target terminations returns 60