Intel 21555 - Manual (Page 107)

21555 Non-Transparent PCI-to-PCI Bridge User Manual 107
Error Handling
12.2 Parity Errors
The 21555 checks, forwards, and generates parity on both the primary and secondary buses. When forwarding
transactions, the 21555 forwards the data parity condition as queued, whether it is bad parity or good parity.
Table 29 describes the 21555’s responses to parity errors.
Table 29. Parity Error Responses (Sheet 1 of 3)
Type of
Error Type of
Transaction PER †
P|S
Action Taken
Address
Parity Error
Primary Bus
Transaction
0 | —
• Responds normally to transaction.
• Sets primary Detected Parity Error bit.
• Forwards transaction with correct parity.
1 | —
• Does not respond to transaction.
• Asserts p_serr_l (when enabled).
• Sets primary Detected Parity Error bit.
Secondary
Bus
Transaction
— | 0
• Responds normally to transaction.
• Sets secondary Detected Parity Error bit.
• Forwards transaction with correct parity.
— | 1
• Does not respond to transaction.
• Asserts s_serr_l (when enabled).
• Sets secondary Detected Parity Error bit.
Data Parity
Error on
Primary
Bus
Downstream
Posted Write
0 | —
• Forwards transaction with parity error.
• Sets primary Detected Parity Error bit.
1 | —
• Forwards transaction with parity error.
• Sets primary Detected Parity Error bit.
• Asserts p_perr_l.
Upstream
Posted Write
0 | —
Trans
action completes normally on primary bus.
1 | —
• Transaction completes on primary bus.
• Sets primary Data Parity Detected bit when p_perr_l is asserted.
1 | 1
• Transaction completes on primary bus.
• Sets primary Data Parity Detected bit when p_perr_l is asserted.
• Asserts s_serr_l when no parity error detected on secondary bus.
† PER: Parity Error Response bit (Primary | Secondary).