Intel 21555 - Manual (Page 108)

108 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Error Handling
Data Parity
Error on
Primary
Bus
Downstream
Delayed
Write
0 | —
• Queues and forwards transaction with parity error.
• Sets primary Parity Error Detected bit.
1 | —
• Returns TRDY# (and STOP# when multiple data phases
requested).
• Transaction not forwarded.
• Sets primary Parity Error Detected bit.
• Asserts p_perr_l.
Upstream
Delayed
Write
0 | — • Transaction completes normally on primary bus.
1 | —
• Transaction completes normally on primary bus.
• Sets primary Data Parity Detected bit when p_perr_l is asserted.
1 | 1
• Transaction completes normally on primary bus.
• Sets primary Data Parity Detected bit when p_perr_l is asserted.
• Asserts s_perr_l when returning s_trdy_l to initiator on secondary
bus (for both CSR and BAR forwarding mechanisms).
Downstream
Delayed
Read
— |
—
The 21555 is returning data, all action is taken by initiator.
Upstream
Delayed
Read
0 | —
• Returns read data with bad parity to initiator (for both CSR and BAR
forwarding mechanisms).
• Sets primary Parity Error Detected bit.
1 | —
• Returns read data with bad parity to initiator (for both CSR and BAR
forwarding mechanisms).
• Sets primary Parity Error Detected bit.
• Sets primary Data Parity Detected bit.
• Asserts p_perr_l.
Configuration
Register or
CSR Write
0 | —
• Writes the data normally.
• Sets the primary Parity Error Detected bit.
1 | —
• Writes the data normally.
• Sets the primary Parity Error Detected bit.
• Asserts p_perr_l.
Configuration
Register or
CSR Read
— |
—
Returns read data normally.
Table 29. Parity Error Responses (Sheet 2 of 3)
Type of
Error Type of
Transaction PER
†
P|S
Action Taken
† PER: Parity Error Response bit (Primary | Secondary).