Motorola MC68VZ328 - Manual (Page 342)

19-26 MC68VZ328 User’s Manual
AC Electrical Characteristics
19.3.21 Exit Self-Refresh Due to CPU Read Cycle (CAS
Latency = 1, Bit RM of DRAM Control Register = 1)
Figure 19-22 shows the timing diagram for the exit self-refresh due to the CPU read cycle. The signal
values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information
about the operation of individual signals can be found in both Chapter 8, “LCD Controller,” and Chapter 7,
“DRAM Controller.”
Figure 19-22. Exit Self-Refresh Due to CPU Read Cycle Timing Diagram
S2 S4 S4 S4 S4 S4 S4 S4 S4 S3
SDCLK
RAS
SCKEN
D[15:0]
CAS
A[16:1]/MD[15:0]
SDA10
CS
WE
DQM
DTACK
S4 S4 S4 S4 S4 S4 S4 S5 S6 S7
Col Row
9
Active
Command
Read
Command