Motorola MC68VZ328 - Manual (Page 12)

xii MC68VZ328 User’s Manual
17.1.3 Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.4 Changing the Speed of Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.5 System Initialization Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.1.6 Application Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.7 Example of Instruction Buffer Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.2 Bootloader Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.3 Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
Chapter 18
Application Guide
18.1 Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.1 Determining the Chip ID and Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.2 8-Bit Bus Width Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.3 Clock and Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.4 Bus and I/O Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
Chapter 19
Electrical Characteristics
19.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3.1 CLKO Reference to Chip-Select Signals Timing. . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.3.2 Chip-Select Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.3 Chip-Select Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3.4 Chip-Select Flash Write Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.5 Chip-Select Timing Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.3.6 DRAM Read Cycle 16-Bit Access (CPU Bus Master). . . . . . . . . . . . . . . . . . . . . . 19-8
19.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master) . . . . . . . . . . . . . . . . . . . . 19-10
19.3.8 DRAM Hidden Refresh Cycle (Normal Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
19.3.9 DRAM Hidden Refresh Cycle (Low-Power Mode) . . . . . . . . . . . . . . . . . . . . . . . 19-12
19.3.10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1 Wait State) . . . . . . . . . 19-13
19.3.11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master). 19-14
19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master) . . 19-16
19.3.13 LCD Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.3.14 Page-Miss SDRAM CPU Read Cycle (CAS Latency = 1) . . . . . . . . . . . . . . . . . 19-19
19.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency = 1) . . . . . . . . . . . . . . . . . . . 19-20
19.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency = 1) . . . . . . . . . . . 19-21
19.3.17 Page-Miss SDRAM CPU Write Cycle (CAS Latency = 1) . . . . . . . . . . . . . . . . . 19-22
19.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency = 1) . . . . . . . . . . . . . . . . . . 19-23
19.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS Latency = 1) . . . . . . 19-24
19.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS Latency = 1, Bit APEN of
SDRAM Power-down Register = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.3.21 Exit Self-Refresh Due to CPU Read Cycle (CAS Latency = 1, Bit RM of DRAM
Control Register = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26
19.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control
Register = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27