Motorola MC68VZ328 User Manual
Page 13

Table of Contents
xiii
Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency = 1) . . . . . . . . 19-28
Page-Miss at Start and in Middle of LCD DMA (CAS Latency = 1) . . . . . . . . . 19-29
Page-Hit LCD DMA Cycle for SDRAM (CAS Latency = 1) . . . . . . . . . . . . . . . 19-30
SPI 1 Master Using DATA_READY Edge Trigger . . . . . . . . . . . . . . . . . . . . . . . 19-32
SPI 1 Master Using DATA_READY Level Trigger . . . . . . . . . . . . . . . . . . . . . . 19-33
SPI 1 Master “Don’t Care” DATA_READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33
SPI 1 Slave FIFO Advanced by SS Rising Edge . . . . . . . . . . . . . . . . . . . . . . . . . 19-34
Mechanical Data and Ordering Information
Index