Motorola MC68VZ328 - Manual (Page 16)

xvi MC68VZ328 User’s Manual
Figure 15-1 PWM 1 and PWM 2 System Configuration Diagram . . . . . . . . . . . . . . . . . . . 15-1
Figure 15-2 PWM 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
Figure 15-3 Audio Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
Figure 15-4 PWM 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Figure 16-1 In-Circuit Emulation Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
Figure 16-2 Typical Emulator Design Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
Figure 16-3 Plug-in Emulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Figure 16-4 Application Development System Design Example. . . . . . . . . . . . . . . . . . . . 16-14
Figure 17-1 Bootstrap Mode Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
Figure 17-2 Bootloader Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
Figure 19-1 CLKO Reference to Chip-Select Signals Timing Diagram . . . . . . . . . . . . . . . 19-3
Figure 19-2 Chip-Select Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
Figure 19-3 Chip-Select Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
Figure 19-4 Chip-Select Flash Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 19-7
Figure 19-5 Chip-Select Timing Trim Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
Figure 19-6 DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Diagram. . . . . 19-9
Figure 19-7 DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Diagram . . . 19-10
Figure 19-8 DRAM Hidden Refresh Cycle (Normal Mode) Timing Diagram . . . . . . . . . 19-12
Figure 19-9 DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Diagram . . . . . . 19-12
Figure 19-10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Diagram . . . . 19-13
Figure 19-11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
Figure 19-12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
Figure 19-13 LCD Controller Timing Diagram (Normal Mode) . . . . . . . . . . . . . . . . . . . . . 19-17
Figure 19-14 LCD Controller Timing Diagram (Self-Refresh Mode) . . . . . . . . . . . . . . . . . 19-18
Figure 19-15 Page-Miss SDRAM CPU Read Cycle Timing Diagram . . . . . . . . . . . . . . . . 19-19
Figure 19-16 Page-Hit SDRAM CPU Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . 19-20
Figure 19-17 Page-Hit CPU Read Cycle for 8-Bit SDRAM Timing Diagram . . . . . . . . . . 19-21
Figure 19-18 Page-Miss SDRAM CPU Write Cycle Timing Diagram . . . . . . . . . . . . . . . . 19-22
Figure 19-19 Page-Hit SDRAM CPU Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . 19-23
Figure 19-20 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM Timing Diagram . . . . . 19-24
Figure 19-21 Page-Hit CPU Read Cycle in Power-down Mode Timing Diagram . . . . . . . 19-25
Figure 19-22 Exit Self-Refresh Due to CPU Read Cycle Timing Diagram. . . . . . . . . . . . . 19-26
Figure 19-23 Enter Self-Refresh Due to No Activity Timing Diagram . . . . . . . . . . . . . . . . 19-27
Figure 19-24 Page-Miss at Starting of LCD DMA for SDRAM Timing Diagram . . . . . . . 19-28
Figure 19-25 Page-Miss at Start and in Middle of LCD DMA Timing Diagram . . . . . . . . 19-29
Figure 19-26 Page-Hit LCD DMA Cycle for SDRAM Timing Diagram . . . . . . . . . . . . . . 19-30
Figure 19-27 SPI 1 and SPI 2 Generic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32