Motorola MC68VZ328 - Manual (Page 201)

Programming Model
I/O Ports 10-31
PGSEL Port G Select Register 0x(FF)FFF433
10.4.9 Port J Registers
Port J is composed of the following four general-purpose I/O registers:
• Port J direction register (PJDIR)
• Port J data register (PJDATA)
• Port J pull-up enable register (PJPUEN)
• Port J select register (PJSEL)
Each signal in the PJDATA register connects to an external pin. As on the other ports, each bit on Port J is
individually configured.
10.4.9.1 Port J Direction Register
The direction register controls the direction (input or output) of the line associated with the PJDATA bit
position. When the data bit is assigned to a dedicated I/O function by the PJSEL register, the DIR bits are
ignored. The settings for the bit positions are shown in Table 10-41.
PJDIR Port J Direction Register 0x(FF)FFF438
BIT 7 6 5 4 3 2 1 BIT 0
SEL5 SEL4 SEL3 SEL2 SEL1 SEL0
TYPE rw rw rw rw rw rw
RESET
0 0 0 0 1 0 0 0
0x08
Table 10-40. Port G Select Register Description
Name Description Setting
Reserved
Bits
7–6
Reserved These bits are reserved and should be set to 0.
SELx
Bits 5–0 Select—These bits select whether the internal chip
function or I/O port signals are connected to the pins. 0 = The dedicated function pins are connected.
1 = The I/O port function pins are connected.
BIT 7 6 5 4 3 2 1 BIT 0
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
TYPE rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 0 0 0
0x00
Table 10-41. Port J Direction Register Description
Name Description Setting
DIRx
Bits 7–0 Direction—These bits control the direction of the pins in
an 8-bit system. They reset to 0. 0 = Input
1 = Output