Motorola MC68VZ328 - Manual (Page 120)

7-10 MC68VZ328 User’s Manual
DRAM Controller Operation
7.2.7 Data Retention During Reset
DRAM needs to retain data during reset, whether it is an external reset or an internal watchdog reset. The
DRAM controller itself has a special design to support this feature. Figure 7-3 illustrates the timing for
data retention.
Figure 7-3. Data Retention for the Reset Cycle
32 kHz
DRAM Sync. with
System Clock
15.6 µs
Sleep with No SYSCLK
Reprogram
DRAM Controller,
External
RESET
(Hardware reset)
Internal
RESET
DRAM
Refresh
DRAM Reset
Port (CSCx, CSDx) Reset
System
Clock
Chip-Selects I/O Port (CSCx,CSDx),
CPCRESET