Altera Quartus II Settings File User Manual
Page 812
• RADP_DFE_FXTAP3_61
• RADP_DFE_FXTAP3_62
• RADP_DFE_FXTAP3_63
• RADP_DFE_FXTAP3_64
• RADP_DFE_FXTAP3_65
• RADP_DFE_FXTAP3_66
• RADP_DFE_FXTAP3_67
• RADP_DFE_FXTAP3_68
• RADP_DFE_FXTAP3_69
• RADP_DFE_FXTAP3_7
• RADP_DFE_FXTAP3_70
• RADP_DFE_FXTAP3_71
• RADP_DFE_FXTAP3_72
• RADP_DFE_FXTAP3_73
• RADP_DFE_FXTAP3_74
• RADP_DFE_FXTAP3_75
• RADP_DFE_FXTAP3_76
• RADP_DFE_FXTAP3_77
• RADP_DFE_FXTAP3_78
• RADP_DFE_FXTAP3_79
• RADP_DFE_FXTAP3_8
• RADP_DFE_FXTAP3_80
• RADP_DFE_FXTAP3_81
• RADP_DFE_FXTAP3_82
• RADP_DFE_FXTAP3_83
• RADP_DFE_FXTAP3_84
• RADP_DFE_FXTAP3_85
• RADP_DFE_FXTAP3_86
• RADP_DFE_FXTAP3_87
• RADP_DFE_FXTAP3_88
• RADP_DFE_FXTAP3_89
• RADP_DFE_FXTAP3_9
• RADP_DFE_FXTAP3_90
• RADP_DFE_FXTAP3_91
• RADP_DFE_FXTAP3_92
• RADP_DFE_FXTAP3_93
• RADP_DFE_FXTAP3_94
• RADP_DFE_FXTAP3_95
• RADP_DFE_FXTAP3_96
• RADP_DFE_FXTAP3_97
• RADP_DFE_FXTAP3_98
• RADP_DFE_FXTAP3_99
Device Support
This setting can be used in projects targeting any Altera device family.
812
XCVR_A10_RX_ADP_DFE_FXTAP3
MNL-Q21005
2015.05.04
Altera Corporation
Quartus Settings File Reference Manual
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)