Ignore_verilog_initial_constructs – Altera Quartus II Settings File User Manual
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IGNORE_VERILOG_INITIAL_CONSTRUCTS
Instructs Analysis & Synthesis to ignore initial constructs and variable declaration assignments in your
Verilog HDL design files. By default, Analysis & Synthesis derives power-up conditions for your design by
elaborating these constructs. This option is provided for backwards compatibility with previous versions
of the Quartus II software that ignored these constructs by default. You can use this option to restore the
previous behavior of your design in the current version of the software.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -entity
set_instance_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -to
entity
Default Value
Off
Example
set_global_assignment -name ignore_verilog_initial_constructs off
110
IGNORE_VERILOG_INITIAL_CONSTRUCTS
MNL-Q21005
2015.05.04
Altera Corporation
Quartus Settings File Reference Manual