Lvds_fixed_clock_data_phase – Altera Quartus II Settings File User Manual
Page 261
LVDS_FIXED_CLOCK_DATA_PHASE
Specifies exact skew compensation. When the fixed clock-to-data skew is known, clock data
synchronization (CDS) can be pre-programmed into the device during configuration. If CDS is pre-
programmed into the device, training patterns do not need to be transmitted to the receiver channels. The
resolution of each pre-programmed setting is 25% of the data period, to compensate for skew up to 50%
of the data period. This option is applied only to input pins that drive the rx_in[] port of the altlvds_rx
megafunction. This option is available for APEX II devices only.
Type
Enumeration
Values
• Default
• Negative 180
• Negative 90
• Positive 180
• Positive 90
• Zero
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_instance_assignment -name LVDS_FIXED_CLOCK_DATA_PHASE -to
MNL-Q21005
2015.05.04
LVDS_FIXED_CLOCK_DATA_PHASE
261
Quartus Settings File Reference Manual
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)