Altera Quartus II Settings File User Manual
Page 811
• RADP_DFE_FXTAP3_18
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• RADP_DFE_FXTAP3_20
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• RADP_DFE_FXTAP3_23
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• RADP_DFE_FXTAP3_3
• RADP_DFE_FXTAP3_30
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• RADP_DFE_FXTAP3_39
• RADP_DFE_FXTAP3_4
• RADP_DFE_FXTAP3_40
• RADP_DFE_FXTAP3_41
• RADP_DFE_FXTAP3_42
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• RADP_DFE_FXTAP3_44
• RADP_DFE_FXTAP3_45
• RADP_DFE_FXTAP3_46
• RADP_DFE_FXTAP3_47
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• RADP_DFE_FXTAP3_49
• RADP_DFE_FXTAP3_5
• RADP_DFE_FXTAP3_50
• RADP_DFE_FXTAP3_51
• RADP_DFE_FXTAP3_52
• RADP_DFE_FXTAP3_53
• RADP_DFE_FXTAP3_54
• RADP_DFE_FXTAP3_55
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• RADP_DFE_FXTAP3_57
• RADP_DFE_FXTAP3_58
• RADP_DFE_FXTAP3_59
• RADP_DFE_FXTAP3_6
• RADP_DFE_FXTAP3_60
MNL-Q21005
2015.05.04
XCVR_A10_RX_ADP_DFE_FXTAP3
811
Quartus Settings File Reference Manual
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)