Altera Stratix II EP2S180 DSP Development Board - Manual (Page 56)

2–48 Core Version a.b.c variable Altera Corporation
Stratix II EP2S180 DSP Development Board Reference Manual
Expansion Interfaces
Figure 2–11. Expansion Prototype Connector Pin Information - J23, J24, J25
Notes to Figure 2–11 :
(1) Unregulated voltage from AC to DC power transformer
(2) Clk from board oscillator
(3) Clk from the Stratix II device via buffer
(4) Clk output from the card to the Stratix II device
RESET_n
R31
P32
M32
N31
L32
M30
N29
L30
GND
K32
K31
K30
K29
J31
H32
G32
G31
F31
E32
GND
R30
P31
M31
N30
L31
M29
N28
L29
NC
GND
GND
GND
J32
GND
H31
NC
F32
L26
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
J24
J23
(1) Vunreg (U54 pin 2)
NC
+3.3V
+3.3V
(2) PROTO1_OSC (U2 pin 6)
(3) PROTO1_CLKIN (U2 pin 17)
(4) PROTO1_CLKOUT (AC14)
+3.3V
+3.3V
+3.3V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
GND
M24
H30
G30
F30
E30
D32
VCC5
E31
H29
G29
F29
E29
D31
1
3
5
7
9
11
13
2
4
6
8
10
12
14
J25