Altera Stratix II EP2S180 DSP Development Board User Manual
Page 36

2–28
Core Version a.b.c variable
Altera Corporation
Stratix II EP2S180 DSP Development Board Reference Manual
Board Components
DQ9
76
AK6
DQ10
77
AJ6
DQ11
79
AM6
DQ12
80
AM7
DQ13
82
AK7
DQ14
83
AJ7
DQ15
85
AM8
DQ16
31
AJ10
DQ17
33
AK8
DQ18
34
AJ8
DQ19
36
AM9
DQ20
37
AF12
DQ21
39
AG10
DQ22
40
AF10
DQ23
42
AG12
DQ24
45
AJ11
DQ25
47
AH11
DQ26
48
AL10
DQ27
50
AM10
DQ28
51
AK12
DQ29
53
AJ12
DQ30
54
AM11
DQ31
56
AM12
DQM0
16
AK5
DQM1
71
AG8
DQM2
28
AH8
DQM3
59
AL5
RAS_N
19
AK4
CAS_N
18
AL8
CKE
67
AL7
CS_N
20
AL6
WE_N
17
AK9
CLK
68
AK16
Table 2–23. SDRAM Device (U39) Pin-Outs (Part 2 of 2)
Pin Name
Pin Number Connects to Stratix II Pin
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)