Altera Stratix II EP2S180 DSP Development Board User Manual
Page 19
Altera Corporation
Core Version a.b.c variable
2–11
Stratix II EP2S180 DSP Development Board Reference Manual
Board Components & Interfaces
shows each clock and its distribution throughout the board.
Figure 2–3. Clock Distribution
lists reference information for the 100-MHz socketed oscillator.
100-MHz
Oscillator
Clock
Distribution
2
CLK_IN_p
CLK_IN_n
DA_EXT_CLK
Expansion
Prototype
Connector
CLK
Buffer
CLK
Buffer
ADC A
ADC B
DAC
DAC
Configuration
Controller
SDRAM
Audio
CODEC
ADC A
Jumper
ADC B
Jumper
DAC A
Jumper
DAC B
Jumper
Clock
Distribution
4
Clock
Distribution
3
Clock
Distribution
1
Expansion
Prototype
Connector
Stratix II
EP2S180F1020C3
Device
Table 2–5. 100-MHz Socketed Oscillator Reference
Item
Description
Board reference
Y1
Part number
ECS-UPO-8PIN 100MHz
Device description
Oscillator
Manufacturer
ECS Inc.
Manufacturer web site
www.ecsxtal.com
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)