Altera Stratix II EP2S180 DSP Development Board - Manual (Page 35)

Altera Corporation Core Version a.b.c variable 2–27
Stratix II EP2S180 DSP Development Board Reference Manual
Board Components & Interfaces
SDRAM Memory (U39 and U40)
The SDRAM devices (U39 and U40) are 2 Micron MT48LC4M32B2
devices with PC100 functionality and self refresh mode. The SDRAM is
fully synchronous with all signals registered on the positive edge of the
system clock.
The SDRAM device pins are connected to the Stratix II device. An
SDRAM controller peripheral is included with the Stratix II DSP
Development Kit, Professional Edition, and allows a Nios II processor to
view the SDRAM devices as a large, linearly-addressable memory.
Table 2–23 lists the Stratix II device pin-outs for SDRAM device U39.
Table 2–23. SDRAM Device (U39) Pin-Outs (Part 1 of 2)
Pin Name Pin Number Connects to Stratix II Pin
A0 25 AD11
A1 26 AD13
A2 27 AB13
A3 60 AE14
A4 61 AB14
A5 62 AC14
A6 63 AD14
A7 64 AE10
A8 65 AB15
A9 66 AC16
A10 24 AB16
A11 21 AE13
BA0 22 AL9
BA1 23 AF11
DQ0 2 AL4
DQ1 4 AJ5
DQ2 5 AH5
DQ3 7 AM4
DQ4 8 AG9
DQ5 10 AH6
DQ6 11 AH7
DQ7 13 AH9
DQ8 74 AM5