Altera Nios Development Board Cyclone II Edition User Manual
Page 37
Altera Corporation
Reference Manual
2–25
May 2007
Nios Development Board Cyclone II Edition
Board Components
F23
5
D6
proto1_io2
J21
48
D9
proto1_io3
J20
4
D5
proto1_io4
F25
49
D10
proto1_io5
F26
3
D4
proto1_io6
N18
27
D11
proto1_io7
P18
2
D3
proto1_io8
G23
28
D12
proto1_io9
G24
23
D2
proto1_io10
G25
29
D13
proto1_io11
G26
22
D1
proto1_io12
H23
30
D14
proto1_io13
H24
21
D0
proto1_io14
J23
31
D15
proto1_io15
H25
35
IOWR_n
proto1_io17
H26
34
IORD_n
proto1_io18
K18
42
IORDY_n
proto1_io19
K24
37
INTRQ
proto1_io22
J25
24
IOCS16_n
proto1_io23
J26
19
A1
proto1_io24
M21
20
A0
proto1_io25
T23
18
A2
proto1_io26
R17
7
CS0_n
proto1_io27
P17
45
DASP
proto1_io28
T18
8
A10
proto1_io29
T17
46
PDIAG
proto1_io30
U26
10
A9
proto1_io31
R19
11
A8
proto1_io32
T19
12
A7
proto1_io33
U20
14
A6
proto1_io34
U21
15
A5
proto1_io35
V26
16
A4
proto1_io36
V25
17
A3
proto1_io37
V24
36
WE_n
proto1_io38
Table 2–13. CompactFlash Pin Table (Continued)
FPGA Pin
CON3 Pin
Pin Function
Board Net Name
(1)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)